Design of a Low Power, High Speed Analog to Digital Pipelined Converter for CMOS Image Sensors Using 0.18μm CMOS Technology

In this work one presented the design a 3bits, 10MSPS of a low power, high speed analog to digital pipelined Converter for CMOS image sensors. The OTA plays an important role in the ADC, because of its conversion rate and power consumption are limited by the performance of the OTA. The designed ADC in this paper employs parallel pipeline architecture based on Double Buffered S&H Circuit with CMOS Switch (SHA), The overall A/D converter performance such as distortion, dynamic range, SFDR and noise are largely dependent on S/H amplifier. The folded cascode OTA functions with a low voltage supply 1.8V and consumes 14.4mW of power, The design is implemented in CMOS 0.18μm, one used a standard architecture composed of two stages, a differential stage of entry, followed of a stage of gain, Besides a Common Mode Feed Back (CMFB) circuit was introduced and some methods are concerned to improve the performance. The simulation shows that the openloop gain of the OTA is 103.94 dB; the phase margin (PM) is 61.06° with the unity gain bandwidth (UGB) of 298.4 MHz .The maximum differential nonlinearity (DNL) is +0.5LSB/LSB and the maximum integral nonlinearity (INL) is 0.4LSB/LSB. The ADC consumes 144mW at 10MS/s sampling rate and the active area of pipeline ADC is about 0.1461 mm2.